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View of Power Efficient VLSI Architecture of 4X4 Modified Column Bypassing Multiplier


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Power Efficient VLSI Architecture of 4X4 Modified Column Bypassing Multiplier

S.Karunakaran1, B. Poonguzharselvi2, T. Logeswaran3, S. Senthil kumar4 , S.SathishKumar5

1Department of ECE, Vardhaman College of Engineering, Shamshabad, Hyderabad-501 218, India.

2Department of CSE, Chaitanya Bharathi Institute of Technology, Gandipet, Hyderabad,-500075, India.

3Department of EEE, Kongu Engineering College, Perundurai, Erode-638060, India.

4Department of EEE, University College of Engineering, Ariyalur, India.

Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam Corresponding author mail id: [email protected]


In this work, 4X4 multiplier which has high speed and less power dissipation is mooted using CMOS VLSI circuits. The crucial parameters in chip design are area, time, power and speed. In the recent scenario, speed and power has made an important concept in Signal Processing practical applications. Various methods are available to optimize .The technique that has been discussed is a high-speed and Low power Multiplier designed based on our Column bypassing technique which is modified and primarily used for reducing the power activity in terms of switching. As this method offers more dynamic power savings, in spite of their interconnections. This paper presents a power efficient VLSI Architecture of 4x4 multiplier. The proposed design is done CMOS Technology in Cadence Virtuoso environment with working voltage supply of ±1.8v


Braun 4X4 multiplier, bypassing coiumn multiplier, low power , High speed


With a view to implement less delay, less power and area wise efficient and mobile design of electronics is typically impugning problem for the designers of hardware in the recent times . Portable mobile phones, cards which are with smart technology, listening aid technology such as PDAs are the example of mobile consumer electronics. The major objective of the above mentioned product are to have good operating capability and also to increase the battery working hours . Less power VLSI circuit techniques used in every hierarchy of system such as system , circuit and architecture level. More power dissipation savings can be obtained it is implemented in system level of design. Large amounts of Power dissipation can be decreased at level of design but it is at cost of delay and over headed area .Pipelining and parallel processing can also be applied at architecture and system level to reduce the power dissipation and to increase the speed . Thus, power dissipation can be lowered by the improvement in fabrication methods such as reduced feature size, very small low voltages, interconnects and insulating material with lesser dielectric constants. Threshold voltage, voltage scaling at the circuit level , sizing of Transistor, power down strategies of network restructuring and style of logic employed predominantly to gain lesser power. Some logic methods useful in the propagation delay reduction and area occupancy reduction..

Applications such as FFT and video processing and filtering are done by digital signal processors. They perform operations like MAC. Multiplication function is the main function in digital signal processors. During multiplication process, transistor undergoes high switching activity. In processor operation such as FFT , Multiplier circuit dissipates nearly thirty percent of power and utilizing fifty percent of chip area. Here by, multiplier circuit consumes more energy and also it takes more time for computation. Different techniques are applied internally and externally in the previous schemes, in order to get energy efficient designs of multiplier. Schemes which are external are linked to the only input data attributes,


where in as an internal scheme originally deals with the technology, system architecture and circuits.

Literature Review

Multiplication is one of the important arithmetic operation which is done by the usual DSP functions including FFT modules and FIR filters. The power consumption is reduced in the multiplier which can reduce a large amount of power dissipation in the present electronics world. The m bit number A and B can be multiplied and defined as follows

Where in the P represents the partial product of the multiplication operation.

Figure 1: Multiplication Process

In the applications of DSP, Multiplication based on array multiplier is a reasonable option because of small circuit and high speed. It depends on regular shift and add operations. Its circuit is set by various stages of full adder cells and AND gates. The circuit might consist of either carry save adders (CSAs) or ripple carry adders (RCAs). For multiplication using RCAs multiplier requires three number of adders and in the worst case it takes 2N+1 adders delay. Multiplier using Carry save adders requires 3N adders to design multiplication so that in the worst case it takes N + 2 adders delay.

Existing Model:

The two numbers which is having n bit that too unsigned can be multiplied by using array parallel multiplier where A is the multiplicand and B is the multiplier.

This multiplier operating in parallel is adapted to implement the multiplication which is unsigned. The Braun multiplier architecture is made up of AND gates array and 3 bit adder


will be proportional to the delay present in the full adders and also the delay present in the final adder which is a ripple carry adder. The dynamic power dissipation of the multiplier resulting from the switching activities can be reduced via bypassing techniques By employing Column bypassing Row bypassing and reversible logic techniques, the dynamic power due to switching activity can be minimised.

Figure 2: Braun Multiplier

Braun multiplier execute very well for the operands which are unsigned and which are lesser than bits of size 16 in the aspect of the power, speed and circuit area. However it is quite elementary structure when compared to the other complex multipliers. Array multiplier could be implemented and power could be analysed for different full adders like CMOS normal full adder, 17 transistor full adder, 15 transistor full adder and SERF 11 transistor full adder and from the comparison the power optimized multiplier will be found out. Four different full adders are used for analysis.

Proposed Modified Column bypassing multiplier:

At the input of the adder cells where we could find the Tri-state buffers and which are thrusted to decrease the transitions of switching if and only when the adder cells are avoided or bypassed. However, Multiplexer is forced to opt sum output sum without avoiding when the bypassing is used. The operation of addition in (i-1)t h column could be avoided for the (i)t h if and only if when the same identical bit is zero in the multiplicand . This operation can be designed by not activating the adder which can be disabled using buffer which can be controlled by ai multiplier bit


Figure 3: Proposed Modified Column Bypassing Multiplier

In any stage, all the inputs of the partial product in the column does not influence the carry.That is the reason why here one 2:1 multiplexer is reduced which has not been required at the output of carry. Therefore, The multiplier based on Column bypassing is simpler to design when it is compared to multiplier by Row Bypassing . In Column Bypassing multiplier, each of the adder is added with tri-state buffers which are only to get the partial product inputs. Tri-state buffer does not need at the input side of the carry in the case of multiplier which is column bypassed. At the output side, Only one 2:1 multiplexer is connected and of to change in between normal path and bypassed path. Carry is not affected in the multiplier which is column bypassed.


Figure 4: Column bypassing multiplier

Simulated Results and Discussions:

Mooted multiplier design and normal multiplier working performance comparison is done using delay and energy consumed. The design is simulated in cadence virtuoso schematic editor Environment. The proposed multiplier design results are congruence with regular design. This proposed structure is for design 16-bit and 8-bit multipliers.

Following figure denotes the schematic of the commonly known as the braun multiplier:

Figure 5 : Existing parallel array multiplier( Braun Multiplier ) The following figure denotes the schematic of the in cadence tool:


Figure 6: proposed modified column bypassing multiplier

Figure 7: Output of the Proposed Modified Column bypassing multiplier

Table 1: Power and delay Analysis of Multipliers

In regular Design, the consumed energy is 11.34nwatts, dissipation close to 7.99µwatts where as the delay equal to 1.9ns. In the design which is mooted, dissipation of power in circuit is


1.3ns. Last, the proposed design results are found to be superior when comparing to the Conventional design.


A high speed and low power multiplier utilising a changed c bypassing column structure is mooted. The mooted experiment gives amazing result in power consumption reduction and delay reduction The Simulated design indicates that multiplier which is mooted design provides a decreasing in power and also less requirement for area .


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“International Journal of Electronics, Electrical and Computation System IJEECS Issn 2348- 117x Vol.6 Issue 9 Sept 2017.

[2] N.N Gopal m Papa Rao,V Shiva “VLSI Design of High Performance Complex Multipliers” International Journal of Engineering Inventions Issn : 2278-7461, Volume 5Issue 1 2016.

[3] Manchal Abuja,Sakshi “Design of BypassingMultiplier with Different Adders Universal journal of Electrical and Electronic Engineering 217-221,2014.

[4] B. Shao and P. Li, Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design. IEEE Transactions on Circuits and Systems I: Regular Papers.vol.62, pp. 1081-1090 (2015)

[5] C. Senthilpari, A.K. Singh, and K. Diwakar. Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell. Microelectronics Journal. vol. 39, pp.

812-821 (2008)

[6] M. Jhamb and H. Lohani. Design, implementation and performance comparison of multiplier topologies in power-delay space. Engineering Science and Technology, an International Journal. (2015)

[7] H. Upadhyay, and S.R. Chowdhury. A High Speed and Low Power 8 × 8 bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates. Journal of Low Power Electronics.

vol. 11, pp. 37-48 (2015)



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